1. Field of the Invention
This invention relates to a semiconductor integrated circuit capable of determining from latched states of a plurality of flip-flops in the semiconductor integrated circuit, whether or not the semiconductor integrated circuit works normally.
2. Description of the Related Art
As a technique in such a field, one described in the following reference, for example, has heretofore been known:
Reference: Japanese Patent Application Laid-Open No. 61-217839
A scan test is carried out to determine whether or not a semiconductor integrated circuit works normally. In one of conventional scan test methods, all the flip-flops provided inside the semiconductor integrated circuit are serially connected to one another to form a single scan path. Data stored in the flip-flops constituting the scan path are shifted so as to be outputted to the outside. Whether or not the semiconductor integrated circuit operates normally, is determined by checking the output data against expected value prepared for the data in advance. This method has a problem in that clocks are required by at least the number of flip-flops upon its determination so that the time required to carry out the scan test is prolonged. In order to solve the problem, a plurality of scan paths in which the flip-flops are serially connected to one another substantially by the same numbers, are formed in the above-described reference. All the outputs from the rearmost ones of the plurality of scan paths are exclusive-ORed. The results of the exclusive OR are checked against the predetermined expected values so as to make a decision as to the operation of the semiconductor integrated circuit.
In such a semiconductor integrated circuit, the number of clocks for shifting the data stored in the respective flip-flops to the outside can be reduced. However, since all the outputs of the rearmost ones of the plurality of scan paths are exclusive-ORed, the expected values corresponding to the exclusive OR become complex.